1. Field of the Invention
The present invention relates to a NAND flash memory.
2. Background Art
For a non-volatile memory cell, such as a NAND flash memory, data is written by applying a high electrical field to the cell to cause trapping of an electron in an oxide film, thereby changing the threshold of the cell. In addition, data is read by utilizing the variation of the threshold. This holds true for multi-level memory cells (see Japanese Patent Laid-Open Publication No. 2001-332093).
A read operation of the conventional NAND flash memory in the shielded bit line architecture will be briefly described.
The source line and the well of a cell are set at a potential “VSS” (0 V), and a potential “VSG” (“VDD”+“Vth”) (about 4 V), which allows transfer of “VDD” (2.5 V), is applied to the gate “BLPRE” of the n-type MOS transistor of the sense amplifier. And, a potential of 0.7 V+Vth is applied to the gate “BLCLAMP” of the n-type MOS transistor that connects the sense amplifier and the bit line to each other, thereby pre-charging the bit line of the cell to a voltage of 0.7 V. (See FIG. 7).
However, not all the bit lines are charged to 0.7 V. The bit lines are alternately charged to 0.7 V and 0 V, and therefore, a half of the bit lines are to be read.
Due to the capacitive coupling, the bit line voltage is affected if the adjacent bit lines voltage is changed during reading. Thus, the bit lines are shielded to prevent data modification caused by data in the adjacent cells.
After the pre-charge, the gate “BLCLAMP” is set at 0 V, and the bit lines are separated from the sense amplifier.
A desired potential “VCGRV” is applied to a word line to be read, a potential “VREAD” (about 5 V) is applied to the other word lines and the drain-side select gate line, and finally the potential “VREAD” is applied to the source-side select gate line.
Thus, if the cell to be read is in the “on” (conductive) state, a cell current flows, and the potential of the bit line approaches 0 V. If the cell to be read is in the “off” (non-conductive) state, no cell current flows, so that the potential of the bit line remains at the pre-charge voltage (0.7 V).
The node “TDC” connected to the latch circuit of the sense amplifier is pre-charged to “VDD”, then the gate “BLCLAMP” is raised again and set at “VSEN” (0.35 V+Vth)
Compared with the capacitance of the bit line, the capacitance of the node “TDC” is small. Therefore, when the cell is in the “on” state, if the voltage of the bit line is lower than 0.35 V, charge sharing occurs, and the voltage at the node “TDC” becomes equal to the voltage of the bit line.
When the cell is in the “off” state, if the voltage of the bit line is equal to 0.7 V, the transistor having the gate “BLCLAMP” remains in the off state because the threshold thereof cannot be exceeded, and thus, the voltage at the node “TDC” remains at “VDD”. By raising the voltage at the gate of the n-type MOS transistor between the latch circuit and the node “TDC”, the voltage at the node “TDC” is transferred to the latch circuit, thereby designating H/L.
The threshold of the cell to be read can be identified by changing the voltage “VCGRV” of the word line of the cell. For example, if the cell has two thresholds, the cell can store two values. If the cell has four thresholds, the cell can store four values.
Thus, if the cell has 16 thresholds, the cell can store 16 values. To store 16 values, the data retention margin of each threshold is reduced. Although the range of thresholds can be expanded to higher thresholds, higher thresholds lead to higher writing voltage and higher reading voltage.
If the writing or reading voltage increases, the writing or reading operation becomes more likely to be disturbed. Therefore, there is a problem that the preset thresholds are also disturbed and shifted. The shift of the thresholds causes erroneous reading.
It can be contemplated that, by setting a negative threshold, the retention margin is improved without increasing the disturbance during reading or writing. Alternatively, this can be achieved by applying a negative potential to the word line.
However, this approach has a disadvantage that the configuration of the well of the Row decoder part has to be modified to transfer the negative potential, so that the number of chip fabrication steps increases.
To overcome the disadvantage, the source line and p-type well of the cell can be biased, thereby making the actual threshold “VGS” of the cell (the voltage of the word line minus the voltage of the source line of the cell) is negative even if a positive voltage is applied to the word line. That is, the threshold distribution can be formed also in the negative region.
However, in this case, the source line and p-type well of whole memory array has to be biased, there can arise a problem that the current consumption increases.
In addition, charging the source line and p-type well of the cell takes additional time, and the reading or writing time increases accordingly (the writing time includes the time required for a verifying operation after writing, as with the reading time).
If the source line and p-type well of the cell array is not biased, only required is the amount of charge enough to charge the selected bit lines.
If the source line and p-type well of the cell is to be biased, an amount of charge is required to bias the source line and p-type well of the cell and non-selected bit lines (shielded bit lines), in addition to the amount of charge required for charging the selected bit lines.
Besides the shielded bit line architecture in which the bit lines are alternately read, there has been proposed a conventional NAND flash memory in which all the bit lines are simultaneously read (see Japanese Patent Laid-Open Publication No. 2006-85839, for example).
Also in the case where all the bit lines are simultaneously read, in order to form a threshold distribution in the negative region, a source line and p-type well of a cell not only in a selected block but also in a non-selected block is biased. In this case, compared with a case where biasing is not carried out, the amount of current required for pre-charging the bit line increases.
Therefore, there can arise a problem that the current consumption increases, as with the shielded bit line architecture.
In addition, as with the shielded bit line architecture, charging the source line and p-type well of the cell takes additional time, and the reading or writing time increases accordingly (the writing time includes the time required for a verifying operation after writing, as with the reading time).